Reduction of the size and the inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of metal-oxide semiconductor (MOS) devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (NMOS) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction.